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FAST CMOS BUS INTERFACE LATCHES
Integrated Device Technology, Inc.
IDT54/74FCT841AT/BT/CT/DT
FEATURES:
* Common features: - Low input and output leakage 1A (max.) - CMOS power levels - True TTL input and output compatibility - VOH = 3.3V (typ.) - VOL = 0.3V (typ.) - Meets or exceeds JEDEC standard 18 specifications - Product available in Radiation Tolerant and Radiation Enhanced versions - Military product compliant to MIL-STD-883, Class B and DESC listed (dual marked) - Available in DIP, SOIC, SSOP, QSOP, CERPACK and LCC packages * Features for FCT841T: - A, B, C and D speed grades - High drive outputs (-15mA IOH, 48mA IOL) - Power off disable outputs permit "live insertion"
DESCRIPTION:
The FCT8xxT series is built using an advanced dual metal CMOS technology. The FCT8xxT bus interface latches are designed to eliminate the extra packages required to buffer existing latches and provide extra data width for wider address/data paths or buses carrying parity. The FCT841T are buffered, 10-bit wide versions of the popular FCT373T function. They are ideal for use as an output port requiring high IOL/IOH. All of the FCT8xxT high-performance interface family can drive large capacitive loads, while providing low-capacitance bus loading at both inputs and outputs. All inputs have clamp diodes to ground and all outputs are designed for low-capacitance bus loading in high-impedance state.
FUNCTIONAL BLOCK DIAGRAM
D0
D1
D2
D3
D4
D5
D8
D9
D LE Q
D LE Q
D LE Q
D LE Q
D LE Q
D LE Q
D LE Q
D LE Q
LE
OE Y0 Y1 Y2 Y3 Y4 Y5 Y8 Y9
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The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(c)1996 Integrated Device Technology, Inc.
JUNE 1996
2571/6
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IDT54/74FCT841AT/BT/CT/DT FAST CMOS BUS INTERFACE LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
OE D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 GND 1 2 3 4 P24-1 5 D24-1 SO24-2 6 SO24-7 7 SO24-8 8 & 9 E24-1 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 LE
D2 D3 D4 NC D5 D6 D7
432 1 28 27 26 25 5 24 6 23 7 8 22 L28-1 9 21 20 10 19 11 1213 14 15 16 17 18
D1 D0 OE NC VCC Y0 Y1
INDEX
Y2 Y3 Y4 NC Y5 Y6 Y7
DIP/SOIC/SSOP/QSOP/CERPACK TOP VIEW
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D8 D9 GND NC LE Y9 Y8
LCC TOP VIEW
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PIN DESCRIPTION
Name DI LE I/O I I Description The latch data inputs. The latch enable input. The latches are transparent when LE is HIGH. Input data is latched on the HIGH-to-LOW transition. The 3-state latch outputs. The output enable control. When OE is LOW, the outputs are enabled. When OE is HIGH, the outputs V I are in highimpedance (off) state.
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FUNCTION TABLE(1)
Inputs LE H H L H H L Internal Output QI YI L H NC L H NC Z Z Z L H NC
OE
H H H L L L
DI L H X L H X
Function High Z High Z Latched (High Z) Transparent Transparent Latched
YI
O I
OE
NOTE: 2571 tbl 02 1. H = HIGH, L = LOW, X = Don't Care, NC = No Change, Z = High Impedance
ABSOLUTE MAXIMUM RATINGS
Symbol Rating Commercial VTERM(2) Terminal Voltage -0.5 to +7.0 with Respect to GND (3) Terminal Voltage VTERM -0.5 to with Respect to VCC +0.5 GND TA Operating 0 to +70 Temperature TBIAS Temperature -55 to +125 Under Bias TSTG Storage -55 to +125 Temperature PT Power Dissipation 0.5 IOUT DC Output Current -60 to +120
(1)
Military -0.5 to +7.0 Unit V
CAPACITANCE (TA = +25C, f = 1.0MHz)
Symbol Parameter(1) CIN Input Capacitance COUT Output Capacitance Conditions VIN = 0V VOUT = 0V Typ. 6 8 Max. Unit 10 pF 12
pF
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-0.5 to VCC +0.5 -55 to +125 -65 to +135 -65 to +150 0.5 -60 to +120
V
C C C
W mA
NOTE: 1. This parameter is measured at characterization but not tested.
NOTES: 2571 lnk 03 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed VCC by +0.5V unless otherwise noted. 2. Input and VCC terminals only. 3. Outputs and I/O terminals only. 6.22 2
IDT54/74FCT841AT/BT/CT/DT FAST CMOS BUS INTERFACE LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Commercial: TA = 0C to +70C, VCC = 5.0V 5%; Military: TA = -55C to +125C, VCC = 5.0V 10%
Symbol VIH VIL II H II L IOZH IOZL II VIK VH ICC Parameter Input HIGH Level Input LOW Level Input HIGH Current(4) Input LOW Current (4) High Impedance Output Current (3-State Output pins) (4) Input HIGH Current(4) Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current VCC = Min., IIN = -18mA
--
Test Conditions(1) Guaranteed Logic HIGH Level Guaranteed Logic LOW Level VCC = Max. VCC = Max. VI = 2.7V VI = 0.5V VO = 2.7V VO = 0.5V VCC = Max., VI = VCC (Max.)
Min. 2.0 -- -- -- -- -- -- -- -- --
Typ.(2) -- -- -- -- -- -- -- -0.7 200 0.01
Max. -- 0.8 1 1 1 1 1 -1.2 -- 1
Unit V V A A A V mV mA
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VCC = Max., VIN = GND or VCC
OUTPUT DRIVE CHARACTERISTICS FOR FCT841T
Symbol VOH Parameter Output HIGH Voltage Test Conditions(1) VCC = Min. IOH = -6mA MIL. VIN = VIH or VIL IOH = -8mA COM'L. IOH = -12mA MIL. IOH = -15mA COM'L. VCC = Min. IOL = 32mA MIL. VIN = VIH or VIL IOL = 48mA COM'L. VCC = Max., VO = GND (3) VCC = 0V, VIN or VO 4.5V Min. 2.4 2.0 -- -60 -- Typ.(2) 3.3 3.0 0.3 -120 -- Max. -- -- 0.5 -225 Unit V V V mA
VOL IOS IOFF
Output LOW Voltage Short Circuit Current Input/Output Power Off Leakage(5)
1
A
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NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc = 5.0V, +25C ambient. 3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second. 4. The test limit for this parameter is 5A at TA = -55C. 5. This parameter is guaranteed but not tested.
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IDT54/74FCT841AT/BT/CT/DT FAST CMOS BUS INTERFACE LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol ICC ICCD Parameter Quiescent Power Supply Current TTL Inputs HIGH Dynamic Power Supply Current (4) Test Conditions(1) VCC = Max. VIN = 3.4V(3) VCC = Max. Outputs Open OE = GND LE = VCC One Input Toggling 50% Duty Cycle VCC = Max. Outputs Open fi = 10MHz 50% Duty Cycle OE = GND LE = VCC One Bit Toggling VCC = Max. Outputs Open fi = 2.5MHz 50% Duty Cycle OE = GND LE = VCC Eight Bits Toggling Min. -- -- Typ.(2) 0.5 0.15 Max. 2.0 0.25 Unit mA mA/ MHz
VIN = VCC VIN = GND
IC
Total Power Supply Current (6)
VIN = VCC VIN = GND VIN = 3.4 VIN = GND
--
1.5
3.5
mA
--
1.8
4.5
VIN = VCC VIN = GND VIN = 3.4 VIN = GND
--
3.0
6.0 (5)
--
5.0
14.0 (5)
NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient. 3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ICC DHNT + ICCD (fCP/2 + fiNi) ICC = Quiescent Current ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) fi = Input Frequency Ni = Number of Inputs at fi All currents are in milliamps and all frequencies are in megahertz.
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IDT54/74FCT841AT/BT/CT/DT FAST CMOS BUS INTERFACE LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT841AT Com'l. Symbol tPLH tPHL Parameter
Propagation Delay DI to YI (LE = HIGH)
FCT841BT Mil. Com'l. Min.(2) 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 2.5 2.5 4.0 Max. 6.5 13.0 8.0 15.5 8.0 14.0 6.0 7.0 -- -- -- 10.0 15.0 13.0 20.0 13.0 25.0 9.0 10.0 -- -- -- 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 2.5 2.5 4.0 Mil. Min.(2) Max. 7.5 15.0 10.5 18.0 8.5 15.0 6.5 7.5 -- -- -- ns ns ns
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Conditions(1) CL = 50pF RL = 500 CL = 300pF(4) RL = 500 CL = 50pF RL = 500 CL = 300pF(4) RL = 500 CL = 50pF RL = 500 CL = 300pF(4) RL = 500 CL = 5pF(4) RL = 500 CL = 50pF RL = 500 CL = 50pF RL = 500
Min.(2) 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 2.5 2.5 4.0
Max. 9.0 13.0 12.0 16.0 11.5 23.0 7.0 8.0 -- -- --
Min.(2) 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 2.5 3.0 5.0
Max.
Unit ns
tPLH tPHL
Propagation Delay LE to YI
ns
tPZH tPZL
Output Enable Time OE to YI
ns
tPHZ tPLZ
Output Disable Time OE to Y
I
ns
tSU tH tW
Data to LE Set-up Time Data to LE Hold Time LE Pulse Width HIGH(3)
NOTES: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. These parameters are guaranteed but not tested. 4. These conditions are guaranteed but not tested.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT841CT Com'l. Symbol tPLH tPHL Parameter
Propagation Delay DI to YI (LE = HIGH)
FCT841DT Mil. Com'l. Max. 4.2 8.0 4.0 8.0 4.8 9.0 4.0 4.0 -- -- -- 6.3 15.0 6.8 16.0 7.3 13.0 6.0 6.3 -- -- -- 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.0 3.0 -- -- -- -- -- -- -- -- -- -- -- Mil. Min.(2) Max. -- -- -- -- -- -- -- -- -- -- -- ns ns ns
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tPLH tPHL
Propagation Delay LE to YI
tPZH tPZL
Output Enable Time OE to YI
tPHZ tPLZ
Output Disable Time OE to Y
I
tSU tH tW
Data to LE Set-up Time Data to LE Hold Time LE Pulse Width HIGH(3)
Conditions(1) CL = 50pF RL = 500 CL = 300pF(4) RL = 500 CL = 50pF RL = 500 CL = 300pF(4) RL = 500 CL = 50pF RL = 500 CL = 300pF(4) RL = 500 CL = 5pF(4) RL = 500 CL = 50pF RL = 500 CL = 50pF RL = 500
Min.(2) 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 2.5 2.5 4.0
Max. Min.(2) 5.5 13.0 6.4 15.0 6.5 12.0 5.7 6.0 -- -- -- 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 2.5 2.5 4.0
Max. Min.(2)
Unit ns
ns
ns
ns
NOTES: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. These parameters are guaranteed but not tested. 4. These conditions are guaranteed but not tested.
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IDT54/74FCT841AT/BT/CT/DT FAST CMOS BUS INTERFACE LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS TEST CIRCUITS FOR ALL OUTPUTS
V CC 500 VIN Pulse Generator RT D.U.T. 50pF CL 500 VOUT 7.0V
SWITCH POSITION
Test Open Drain Disable Low Enable Low All Other Tests Open
2571 lnk 11 DEFINITIONS: CL= Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Switch
Closed
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SET-UP, HOLD AND RELEASE TIMES
DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. tSU 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V
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PULSE WIDTH
tH
LOW-HIGH-LOW PULSE tW HIGH-LOW-HIGH PULSE
1.5V
tREM
1.5V
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tSU
tH
PROPAGATION DELAY
ENABLE AND DISABLE TIMES
ENABLE DISABLE 3V 1.5V 0V 3.5V 0.3V tPHZ 0.3V 1.5V 0V VOH 0V
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SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL
3V 1.5V 0V VOH 1.5V VOL 3V 1.5V 0V
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CONTROL INPUT tPZL OUTPUT NORMALLY LOW OUTPUT NORMALLY HIGH SWITCH CLOSED tPZH SWITCH OPEN 3.5V 1.5V tPLZ
VOL
NOTES: 1. Diagram shown for input Control Enable-LOW and input Control DisableHIGH 2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns
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IDT54/74FCT841AT/BT/CT/DT FAST CMOS BUS INTERFACE LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
FCT IDT XX XXXX Temp. Range Device Type X Package X Process Blank B P D E L SO PY Q 841AT 841BT 841CT 841DT Commercial MIL-STD-883, Class B Plastic DIP CERDIP CERPACK Leadless Chip Carrier Small Outline IC Shrink Small Outline Package Quarter-size Small Outline Package 10-Bit Non-Inverting Latch
54 74
-55C to +125C 0C to +70C
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